The present invention, as recited by the claims, covers an electronic system for testing a set of multiple chips concurrently or sequentially in selectable subsets under program control to limit chip power dissipation. In the prior art, a related electronic system for testing chips is disclosed in U.S. Pat. No. 5,390,129. This prior art system is assigned to Unisys Corporation, who also is the assignee of the present invention.
A simplified block diagram of the prior art chip testing system is shown in FIG. 2 of patent ""129. That system includes a computer 50 which is coupled via a time-shared bus 52 to a plurality of driver boards 100; and each driver board 100 is coupled to a respective burn-in board 500 which holds several integrated circuit chips that are to be tested.
In operation, the computer 50 sequentially sends each driver board 100 a separate set of test data patterns that are used to test the chips. These test data patterns are stored on each driver board in a large SRAM which is shown in FIG. 3 by reference numeral 107 and is shown in greater detail in FIG. 9 by reference numeral 145. Which particular driver board receives and stores the test data patterns at any one time is determined by an address circuit 100A that is on the driver board, as is shown in the FIG. 2 block diagram.
After the test data patterns are stored in the SRAM 145 on all of the driver boards 100, then the chips on all of the burn-in boards 500 can be tested in parallel. To do that, the test patterns are concurrently read from all of the SRAMs and sent through respective output driver modules 164, as shown in FIG. 14, to the chips on all of the burn-in boards 500.
One particular feature of the chip testing system in patent ""129 is that each burn-in board includes an ID code which identifies the types of chips that are to be tested on the board. That ID code is sensed by the driver board 100 and sent to the computer 50; and in response, the test data patterns which the computer 50 sends to the driver board are tailored to the ID code that is sensed.
However, the chip testing system in patent ""129 also has some major limitations which are imposed by the FIG. 2 architecture. For example, the computer 50 is the sole source of the test data patterns for all of the driver boards 100. Consequently, the speed of operation of the chip testing system is limited because the computer 50 can only send the test data patterns to a single driver board at a time over the bus 52.
Another limitation of the chip testing system in patent ""129 is that each driver board 100 always tests all of the chips on a burn-in board 500 concurrently. However, each burn-in board inherently has a limit on the total amount of power which the chips on this board can dissipate. Thus, in order to keep the total power dissipation on each burn-in 500 board below a certain limit, the number of chips on each burn-in board must be decreased as the maximum power dissipation per chip increases.
Still another limitation of the chip testing system in patent ""129 is that the stored test data patterns in the large SRAM 145 on each driver board can make very inefficient use of SRAM memory cells. FIG. 9 of patent ""129 shows that each SRAM 145 receives nineteen address bits and has eight data output bits; and thus the SRAM 145 on each driver circuit has eight million memory cells. But, certain types of chips are tested by sending them sequences of serial bit streams that vary in number with time. Thus, if an SRAM 145 sends four bit streams during one time interval and sends only two bit streams during other time intervals, then half of the SRAM is wasted when the two bit streams are being sent.
Accordingly, a primary object of the chip test testing system which is disclosed herein is to address and overcome all of the above limitations.
The present invention, as recited by the claims, covers one aspect of the disclosed chip testing system which addresses the above limitation of testing chips such that their total power dissipation is kept below a certain limit. In accordance with the present invention, a system for testing integrated circuit chips is comprised of a signal generator which generates a clock signal; a control circuit having a first input which receives the clock signal, a second input for receiving commands, and multiple outputs; a command source for sending programmable sequences of the commands to the second input of the control circuit; and a means in the control circuit for selecting particular outputs in response to the commands and passing the clock signal from the first input to only the selected outputs.
All of the outputs of the control circuit are coupled through respective clock transmitters to different chips which are to be tested. So in response to the programmable commands, the clock signal can be sent sequentially to the chips that are to be tested, in selectable subsets. By such sequencing, the total power dissipation of the chips that are tested can be regulated when the chips are of a type that dissipate a large amount of power when they receive the clock signal, but dissipate substantially less power when they do not receive the clock signal. Such chips include, for example, CMOS microprocessor chips and CMOS memory chips.